ARM9
ARM9 cores introduced a five-stage pipeline and Harvard architecture.
ARM9 refers to a family of 32-bit RISC ARM processor cores that ARM Holdings licenses for use in microcontrollers. The family includes the ARM9TDMI, ARM940T, ARM9E-S, ARM966E-S, ARM920T, ARM922T, ARM946E-S, ARM9EJ-S, ARM926EJ-S, ARM968E-S, and ARM996HS. These cores were introduced between 1998 and 2006, and ARM no longer recommends them for new integrated circuit designs, suggesting newer Cortex-M cores instead.
A key architectural change in this generation was the shift from a von Neumann (Princeton) architecture to a modified Harvard architecture. This design uses separate instruction and data buses and caches, which can significantly boost potential speed. Most chips that integrate these cores implement them as modified Harvard architecture devices, combining the two address buses on the far side of the separate CPU caches and tightly coupled memories. The ARM9 family splits into two subfamilies, each implementing a different version of the ARM architecture.
Compared to ARM7 cores, ARM9 cores offer several improvements that come from using more transistors. Clock frequency roughly doubles because the instruction pipeline expands from three stages to five. Many unmodified ARM7 binaries run about 30% fewer cycles on ARM9 cores. Faster loads and stores are a major reason; many instructions now complete in a single cycle, helped by the modified Harvard architecture (which reduces bus and cache contention) and the new pipeline stages. The pipeline also exposes interlocks, allowing compiler optimizations to reduce stalls between stages. Some ARM9 cores add "Enhanced DSP" instructions, like multiply-accumulate, for more efficient digital signal processing. The switch to a non-unified cache means instruction fetches do not evict data and vice versa. ARM9 cores have separate data and address bus signals, which chip designers use in various ways. Typically, they connect at least part of the address space in a von Neumann style—used for both instructions and data—often to an AHB interconnect that links to a DRAM interface and an External Bus Interface for NOR flash memory. Such hybrids are no longer pure Harvard architecture processors.
ARM Holdings does not manufacture or sell CPU devices based on its own designs. Instead, it licenses the processor architecture to interested parties under various terms, with different costs and deliverables.
Quick Facts
- Designfirm
- ARM Holdings
- Arch
- ARM (32-bit), / Thumb (16-bit)
- Microarch
- ARMv4T
Facts from the source article.
Lore & Background
The ARM9 core family succeeded the ARM7 cores, shifting from a three-stage instruction pipeline to a five-stage one, which allowed clock speed to be approximately doubled on the same silicon fabrication process. Many unmodified ARM7 binaries were measured as taking about 30% fewer cycles to execute on ARM9 cores, helped by faster loads and stores, the modified Harvard architecture, and new pipeline stages that exposed pipeline interlocks for compiler optimizations. Some ARM9 cores incorporated Enhanced DSP instructions, such as a multiply-accumulate, to support more efficient digital signal processing algorithms.
ARM9 cores are no longer recommended for new IC designs; newer alternatives are ARM Cortex-M cores. ARM Holdings neither manufactures nor sells CPU devices based on its own designs, but licenses the processor architecture to interested parties. Integrated device manufacturers receive the ARM Processor IP as synthesizable RTL written in Verilog, allowing them to perform architectural level optimizations and extensions for custom design goals such as higher clock speed, very low power consumption, or instruction set extensions.
The ARM9TDMI is a successor to the ARM7TDMI core, based on the ARMv4T architecture, and includes cores like the ARM920T with 16 KB each of I/D cache and an MMU, the ARM922T with 8 KB each of I/D cache and an MMU, and the ARM940T with cache and a Memory Protection Unit. The ARM9E and ARM9EJ implement the ARMv5TE architecture with DSP-esque instruction set extensions and a doubled multiplier unit width, halving time for most multiplication operations. The ARM926EJ-S includes ARM Jazelle technology for direct execution of 8-bit Java bytecode in hardware.
Reader's Guide
The ARM9 core family represents a significant architectural transition in ARM's history, moving from von Neumann to modified Harvard architecture and from a three-stage to a five-stage pipeline. These changes enabled substantial performance improvements over ARM7 cores, including roughly double the clock speed on the same process and about 30% fewer cycles for many unmodified ARM7 binaries. The introduction of separate instruction and data caches reduced bus and cache contention, while the new pipeline stages allowed compiler optimizations to reduce blockage between stages.
The ARM9 family's licensing model, where ARM Holdings provides an integratable hardware description and software development toolset to licensees, enabled widespread adoption across many manufacturers. Chips based on ARM9 cores appeared in a diverse range of products, from graphing calculators like the TI-Nspire CX and CX II to Nintendo DS and DSi processors, baseboard management controllers, and numerous system-on-chip designs from companies such as Atmel, Samsung, Texas Instruments, NXP, and STMicroelectronics. The family's support for both ARM and Thumb instruction sets, and in some cases Java bytecode execution, made it versatile for embedded applications. However, ARM9 cores are no longer recommended for new designs, having been superseded by ARM Cortex-M cores.
Did You Know?
- The TI-Nspire CX (2011) and CX II (2019) graphing calculators use an ARM926EJ-S processor clocked at 132 and 396 MHz respectively.
- The Nintendo DS used an ARM946E-S core, while the Nintendo DSi used the same core but clocked at 133 MHz instead of 67 MHz.
- Some ARM9 cores incorporate Enhanced DSP instructions such as a multiply-accumulate for digital signal processing algorithms.
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