ARM Cortex-R

Lore & Background

The ARM Cortex-R family implements the R profile of the ARM architecture, designed for high-performance hard real-time and safety-critical applications. It is similar to the A profile for applications processing but adds features for fault tolerance and deterministic behavior. These features include tightly coupled memory with guaranteed fast access, increased hardware exception handling, hardware division instructions, a memory protection unit (MPU), deterministic interrupt handling with fast non-maskable interrupts, ECC on L1 cache and buses, and dual-core lockstep for CPU fault tolerance.

The Armv8-R architecture includes virtualization features similar to those introduced in the Armv7-A architecture, providing two stages of MPU-based translation to isolate multiple operating systems under a hypervisor. Prior to the R82, introduced on 4 September 2020, the Cortex-R family lacked a memory management unit (MMU) and could not use virtual memory, making them unsuitable for full-featured Linux. Many real-time operating systems (RTOS) regarded the lack of an MMU as a feature for total control. On the R82, it may be possible to run a traditional RTOS in parallel with a paged OS such as Linux, where Linux uses the MMU for flexibility while the RTOS locks the MMU into direct translation mode on its assigned pages for predictability.

Reader's Guide

The ARM Cortex-R family occupies a distinct niche in the processor landscape, bridging the gap between application processors and microcontrollers. Its significance lies in providing deterministic, fault-tolerant computing for systems where failure can cause severe injury or loss of life. The family's inclusion of features such as tightly coupled memory, ECC, and dual-core lockstep directly addresses the requirements of hard real-time and safety-critical applications. The addition of an MMU in the Cortex-R82 expanded the family's capabilities, potentially allowing coexistence of a paged OS like Linux with a traditional RTOS on the same core. ARM Holdings does not manufacture or sell CPU devices based on its own designs but licenses the core designs as synthesizable RTL written in Verilog, allowing integrated device manufacturers to perform architectural-level optimizations and extensions. The Cortex-R family has achieved formal certification for the most demanding safety levels: the Cortex-R52+ and Cortex-R5/R5F cores have been certified to Automotive Safety Integrity Level D (ISO 26262) and Safety Integrity Level 3 (IEC 61508). These certifications make the family suitable for applications such as electronic braking systems, medical devices, programmable logic controllers, electronic control units, robotics, avionics, motion control, and advanced peripheral devices like flash memory controllers and network interface controllers.

Did You Know?

• The Cortex-R family implements the ARM Real-time (R) profile, one of three architecture profiles alongside Application (A) and Microcontroller (M).
• Prior to the Cortex-R82, no Cortex-R core included a memory management unit (MMU), making them unable to use virtual memory.
• The Cortex-R52+ processor IP core achieved Automotive Safety Integrity Level D certification on 22 April 2024.
• ARM Holdings licenses core designs as synthesizable RTL written in Verilog, allowing manufacturers to perform custom optimizations.