ARM Cortex-M
32-bit RISC cores for low-cost, energy-efficient embedded devices.
The ARM Cortex-M is a family of 32-bit RISC ARM processor cores licensed by ARM Limited, optimized for low-cost and energy-efficient integrated circuits. These cores have been embedded in tens of billions of consumer devices, most often as the main component of microcontroller chips, though they are also embedded inside other types of chips such as ASICs, ASSPs, FPGAs, and SoCs. The family includes Cortex-M0, Cortex-M0+, Cortex-M1, Cortex-M3, Cortex-M4, Cortex-M7, Cortex-M23, Cortex-M33, Cortex-M35P, Cortex-M52, Cortex-M55, and Cortex-M85.
Quick Facts
- Arch
- ARMv6-M (Thumb-1 (most), / Thumb-2 (some))
Facts from the source article.
Lore & Background
The Cortex-M family is designed for use in microcontrollers, ASICs, ASSPs, FPGAs, and SoCs. Unlike Cortex-A cores, Cortex-M cores lack a memory management unit (MMU) for virtual memory, making them unsuitable for full-fledged operating systems; programs instead run bare metal or on real-time operating systems. The cores have gradually displaced 8-bit microcontrollers in applications benefiting from 32-bit math operations, and have replaced older legacy ARM cores such as ARM7 and ARM9. ARM Limited licenses the processor architecture to integrated device manufacturers, providing synthesizable RTL (Verilog) and a software development toolset, allowing licensees to perform architectural optimizations and extensions such as higher clock speed, low power consumption, and instruction set extensions.
Reader's Guide
The Cortex-M family's significance lies in its widespread adoption in embedded systems, from microcontrollers to hidden controllers within SoCs (e.g., power management, I/O, touch screen, and sensor controllers). Its binary instruction upward compatibility from ARMv6-M through ARMv8.1-M allows software written for lower-end cores to run on higher-end ones without modification. The family's optional features—such as the SysTick timer, bit-band memory mapping, memory protection unit, tightly-coupled memory, and floating-point units—enable customization for diverse applications. The Cortex-M0/M0+/M1/M23 are designed for minimal silicon die size with the fewest instructions, while higher-end cores add DSP instructions, hardware integer divide, saturation arithmetic, and TrustZone security extensions. The cores' interrupt latency varies with architecture (Harvard vs. Von Neumann) and optional security extensions. The family's legacy includes replacing 8-bit microcontrollers and older ARM cores in billions of devices, with the embedded wear-leveling controller inside most SD cards or flash drives being an 8051 microcontroller or ARM CPU.
Did You Know?
- The Cortex-M family includes 12 cores: M0, M0+, M1, M3, M4, M7, M23, M33, M35P, M52, M55, and M85.
- Cortex-M cores have no memory management unit (MMU), so they cannot run full-fledged operating systems.
- The SysTick timer is optional on M0/M0+/M1/M23 but extremely rare to find a Cortex-M microcontroller without it.
- Bit-band mapping allows individual bits in memory to be set or cleared without a read-modify-write sequence.
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