Microprocessors, Part 2 Codexery

Apollo PRISM

A VLIW CPU that briefly held the title of fastest microprocessor.

Apollo PRISM

The Apollo PRISM (Parallel Reduced Instruction Set Multiprocessor) powered the company's DN10000 series workstations and was, for a time, the fastest microprocessor on the market, delivering performance comparable to a significant fraction of a Cray-1 in a desktop machine. Its architecture was based on what is now called a VLIW (Very Long Instruction Word) design, which set it apart from the purer RISC approaches that dominated the era around 1988. The system relied heavily on its compilers, which spent extra time during compilation to manage registers and schedule instructions. By handling instruction scheduling in software, the design avoided the complexity of dynamic scheduling found in superscalar chips like Digital Equipment Corporation's Alpha. In a VLIW approach, the compiler finds safe instruction pairs and packages them into longer words. For a two-functional-unit CPU like PRISM, the compiler would pair instructions; the CPU would then split them apart and feed each to its respective unit. This kept the CPU logic simple as units were added, but it also tightly coupled compiled code to the processor's exact configuration—adding functional units in a new generation would require all software to be recompiled. The Apollo compilers were the first commercial compilers to use single static assignment techniques. PRISM was a pure 32-bit design, featuring thirty-two 32-bit integer registers and thirty-two 64-bit floating-point registers (which could also be viewed as sixty-four 32-bit registers). It could dispatch one integer instruction per cycle, or one integer plus one floating-point instruction. The floating-point unit could combine an add and a multiply into a single instruction. The compiler aimed to always pair or triple instructions to keep all units busy, but if no safe pair was found, it would issue a lone integer instruction. PRISM was one of the first designs to include a multiply with add, subtract, or truncate in a single five-operand instruction, leading to its description as a three-issue CPU. Development of the PRISM began in 1986, and it was announced in March 1988. The one-to-four-CPU Apollo DN10000 workstation reached customers in October 1988. The "DN" stood for "Domain Node," referencing the Domain/OS operating system. The PRISM was a multi-chip CPU board, not a single microprocessor, a common approach for high-end CPUs at the time.

Year announced
March 1988
Year delivered
October 1988
Design started
1986
Integer registers
32 × 32-bit
Floating-point registers
32 × 64-bit (overlaid by 64 × 32-bit)
Instruction dispatch
One integer or one integer plus one floating-point per clock cycle
Systems sold
Approximately 1,000 DN10000 systems

Lore & Background

The PRISM design exercise began in 1986, and the system was announced in March 1988, with the one-to-four-CPU Apollo DN10000 workstation reaching customers in October 1988. The 'DN' in the workstation name stood for 'Domain Node', referencing the Domain/OS operating system. The PRISM was a multi-chip CPU board, not a single microprocessor, a common arrangement for high-end CPUs at the time; various chips were fabricated by Bipolar Integrated Technology and used in other systems. Digital Equipment Corporation also engineered a RISC chip named PRISM during the same era, but that project was canceled in 1988, and never entered production.

Reader's Guide

The PRISM's VLIW design offloaded instruction scheduling to the compiler, which examined code and selected 'safe' instructions to package into longer words. For a CPU with two functional units, the compiler would find pairs of safe instructions and stuff them into a single larger word; inside the CPU, the instructions were split apart and fed to the selected units. This minimized logical changes to the CPU as functional units were added, but tied compiled code tightly to the processor design—adding functional units in a new generation required recompilation. The Apollo compilers were the first commercial compilers to use single static assignment techniques. In practice, the PRISM was much faster than the Intel i860, another VLIW design of the era, which proved notoriously difficult to extract performance from. Benchmarking indicated the DN10000 system had around twice the performance of the MIPS M/2000-6, and the PRISM CPU was described as having more than half the performance of 'the largest IBM mainframe CPU' for some users, raising the possibility of using a four-processor DN10000 workstation in place of mainframe-based computing.

Did You Know?

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