F-14 CADC
Early MOS-based flight control computer for the F-14 Tomcat.
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The Central Air Data Computer (CADC) was a multi-chip integrated flight control system built by Garrett AiResearch for early F-14 Tomcat fighters. It worked out altitude, vertical speed, air speed, and Mach number using inputs from pitot and static pressure sensors and a temperature gauge. The CADC was developed between 1968 and 1970, making the F-14 the first military aircraft to rely on custom digital integrated circuits.
The system used MOS custom integrated circuits and has been called the first microprocessor chipset, though the Intel 4004—the first commercial microprocessor—came out around the same time. The 4004 lacked the computing power and interfacing needed for flight control, and chip technology at the time couldn't fit enough transistors onto a single chip for such a system.
The CADC was designed by a team led by Steve Geller and Ray Holt, with help from the startup American Microsystems. Design work began in 1968 and finished in June 1970, beating out several electromechanical systems also built for the F-14.
The Navy kept the design classified until 1998. Holt wrote an article about it for Computer Design magazine in 1971, but the Navy classified that too, releasing it only in 1998. Holt later told the story in his autobiography The Accidental Engineer.
Components
The CADC included an analog-to-digital converter, several quartz pressure sensors, and a number of MOS-based microchips. Inputs came from the primary flight controls, switches, static and dynamic air pressure (to calculate stall points and airspeed), and a temperature gauge. Outputs controlled the wing sweep, maneuver flaps and slats, and limited allowable control inputs.
The core of the CADC was the MP944 chip set, which ran at 375 kHz and executed 9,375 instructions per second. It used a 20-bit fixed-point-fraction two's complement number system. The complete system used 28 chips with 74,442 transistors, built from six unique dual in-line package (DIP) chips.
These chips were arranged into three modules. Each module had ROMs that sent microinstructions and constants serially to that module's SLU, which routed data inputs to the module's computation unit (a PMU, PDU, or SLF). Results were written into the module's RAS and could be routed via the SLUs to any other module. Each module formed its own pipeline and could run independently, making it easy to add more modules.
Quick Facts
- Development period
- 1968 to 1970
- Clock speed
- 375 kHz
- Instructions per second
- 9375
- Number system
- 20-bit fixed-point-fraction two's complement
- Total transistors
- 74442
- Number of chips
- 28
Facts from the source article.
Lore & Background
Design work on the CADC started in 1968 and was completed in June 1970, beating a number of electromechanical systems also designed for the F-14. The team was led by Steve Geller and Ray Holt, supported by the startup American Microsystems. The system was classified by the Navy until 1998. In 1971, Holt wrote an article about the system for Computer Design magazine, which the Navy classified and released in 1998.
The CADC consisted of an analog-to-digital converter, several quartz pressure sensors, and a number of MOS-based microchips. Inputs included primary flight controls, switches, static and dynamic air pressure, and a temperature gauge. Outputs controlled the wing sweep, maneuver flaps and slats, and limited allowable control inputs.
The MP944 chip set ran at 375 kHz, executing 9375 instructions per second, based on a 20-bit fixed-point-fraction two's complement number system. The 28-chip system used six unique dual in-line package chips. The system arranged these chips into three modules, each with ROMs that serially sent microinstructions and constants to a SLU, which routed data to a computation unit (PMU, PDU, or SLF).
Results were written into a RAS and routed via SLUs to any module. Each module formed its own pipeline and could be used without the others, enabling expansion with additional modules. Multiple pipelines worked simultaneously, a parallel computing technique called 'pipeline concurrency'.
Reader's Guide
The CADC is historically significant as an early implementation of MOS custom integrated circuits in a military flight control system. It has been claimed as the first microprocessor chipset, though the first commercial microprocessor chip was the contemporary Intel 4004. The 4004 did not have nearly the computing power or interfacing capability required to perform the functions of the CADC. At the time, the best integrated circuit technology lacked the scale necessary to build a single-chip microprocessor for a flight control system.
The CADC's modular pipeline architecture allowed parallel computation and easy expansion, demonstrating an early form of pipeline concurrency. Its classification by the Navy until 1998 kept its technical details from public knowledge for decades. The system's use of a 20-bit fixed-point-fraction two's complement number system and its 375 kHz clock rate reflect the state of digital electronics in the late 1960s and early 1970s.
Frequently Asked Questions
What did the F-14 CADC actually calculate?
It derived altitude, vertical speed, airspeed, and Mach number by interpreting signals from pitot and static pressure sensors plus a temperature gauge. This gave the aircraft a single, unified digital picture of its flight state.
What were the CADC's key hardware specifications?
The system clocked at 375 kHz, executed roughly 9,375 instructions per second, and operated on a 20-bit fixed-point two's-complement number system. Its 28 chips contained a combined total of 74,442 transistors.
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Sources
Compiled from Wikipedia and the sources listed below. Text from Wikipedia is available under CC BY-SA 4.0; this entry is adapted from it.
- Wikipedia: F-14 CADC (CC BY-SA 4.0).
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