7 nm process

Lore & Background

In the early 2000s, researchers began demonstrating 7 nm level MOSFETs, with an IBM team fabricating a 6 nm silicon-on-insulator (SOI) MOSFET in 2002, and NEC's researchers fabricating a 5 nm MOSFET in 2003. In July 2015, IBM announced the first functional transistors with "7nm" technology using a silicon-germanium process. TSMC started risk production of its "7nm" branded process (N7) in 2016, with volume production beginning in 2018, and Samsung began mass production of its "7nm" (7LPP) devices in 2018.

Reader's Guide

The "7 nm process" marks a significant shift in semiconductor naming conventions, where the node name no longer corresponds to any specific physical dimension on the chip. This divergence arose because new lithography processes no longer uniformly shrank all features, and previous ITRS and IRDS standards lacked sufficient guidance on naming. The node enabled the first mass-market 7 nm mobile processor, the Apple A12 Bionic (released September 2018), and powered AMD's Rome server processors and Matisse desktop CPUs. TSMC's N7 node was used for multiple products, while GlobalFoundries stopped development of 7 nm chips in August 2018 citing cost. Intel later rebranded its equivalent node as "Intel 7." The node's legacy includes the introduction of extreme ultraviolet lithography (EUV) in later variants like N7+ and N6.

Did You Know?

• The first volume production of a "7 nm" branded process was TSMC's N7 process in 2018, not 2016; the 256Mbit SRAM was a demonstration, not volume production.
• The Apple A12 Bionic was the first 7 nm chip for mass market use, announced in September 2018.
• GlobalFoundries stopped development of "7nm" chips in August 2018, citing cost.
• Intel's "10nm Enhanced Superfin" node was later rebranded as "Intel 7" and was roughly equivalent to TSMC's N7 process.

The Name That Meant Nothing

Since 1997, the "7 nm" label has had no direct correspondence to any measurable physical feature on a chip. The International Roadmap for Devices and Systems (IRDS), successor to the older ITRS, attempted to standardize node definitions, but the reality was that modern lithography no longer shrank every dimension uniformly. By the late 2010s, "7 nm" had become essentially a marketing generation marker rather than a specification. Foundries branded their processes differently from the actual gate pitches, metal pitches, or gate lengths they achieved, creating a growing gap between the name and the silicon underneath. The 2021 IRDS Lithography standard, written retrospectively, finally tabulated example dimensions for the node, but by then the divergence was well established. What consumers and engineers call "7 nm" is, in practice, a commercial shorthand for a particular generation of FinFET-based multi-gate MOSFET technology, with no single number defining its geometry.

The Production Race

The path from laboratory demonstration to volume manufacturing at the 7 nm node was a tightly contested sprint among a handful of foundries. TSMC moved first, beginning risk production of 256Mbit SRAM chips on its N7FF process in April 2017 using DUV immersion lithography, then ramping to volume production by April 2018 and full mass production by June of that year. Samsung followed, announcing its 7LPP process in May 2018 and entering risk production of a second-generation variant by October 2018, with mass production targeted for 2019; ASML supplied the EUV lithography tools. GlobalFoundries had announced trial production for late 2017 and risk production for early 2018, but in August 2018 it abandoned the 7 nm effort entirely, citing cost. Intel, meanwhile, had announced Fab 42 in Chandler, Arizona, in February 2017 for what would become its 7 nm process, though it had not yet published feature-length targets. The node's transistor density ended up closely matching Intel's "10 nm Enhanced Superfin," later rebranded "Intel 7," underscoring how much the names had decoupled from physical reality.

From Silicon to Shelves

The 7 nm node crossed from foundry floorboards into consumer hands in the latter half of 2018, and the first wave was overwhelmingly mobile. Huawei unveiled its Kirin 980 on August 31, 2018, and Apple followed days later at its September event with the A12 Bionic; both were fabricated by TSMC, and the A12 Bionic reached mass-market consumers first. The node's reach expanded dramatically in 2019 when AMD brought it to the server and desktop segments. Its "Rome" EPYC 2 processors, built on TSMC's N7 node, offered up to 64 cores and 128 threads for datacenter workloads, while the "Matisse" desktop line delivered up to 16 cores and 32 threads. Notably, the I/O dies in those multi-chip modules were not 7 nm: Rome's used GlobalFoundries' 14HP process and Matisse's used the 12LP+ process, illustrating how a single product could span multiple nodes. AMD also placed its Radeon RX 5000 graphics series on TSMC's N7, extending the node's footprint into consumer GPU silicon at this scale.

The Physics Beneath the Brand

At its core, the 7 nm node is a FinFET implementation—a multi-gate MOSFET architecture in which the channel is shaped into a fin and surrounded by gates on multiple sides, giving better electrostatic control than planar transistors. The research lineage stretches back to the early 2000s: an IBM team including Bruce Doris and colleagues fabricated a 6 nm silicon-on-insulator MOSFET, and NEC researchers Hitoshi Wakabayashi and Shigeharu Yamagami pushed further with a 5 nm device in 2003. In July 2015, IBM announced the first functional 7 nm transistors using a silicon-germanium process. TSMC's February 2017 milestone—256Mbit SRAM cells with a 0.027 square-micrometer area—yielded a normalized F² value of 550, a metric the IRDS used to benchmark density. Lithography strategy varied: TSMC planned DUV immersion for N7FF and EUV multi-patterning for the N7FF+ variant, while Samsung leaned on ASML's EUV tools. Intel had predicted that by this node, III–V semiconductors would need to replace silicon in transistors, foreshadowing a materials shift the industry has yet to fully realize.