45 nm process

Lore & Background

The 45 nm process was a pivotal node in the semiconductor industry, as chipmakers faced the challenge of patterning features smaller than the wavelength of light used in lithography (193 nm and 248 nm). To overcome this, techniques such as larger lenses and double patterning were employed. Intel, for example, used a line-cutting double patterning method for its 45 nm process, as immersion lithography was not used. The node also saw the introduction of high-κ dielectric materials and metal gates, which Intel considered a fundamental change in transistor design, reducing gate leakage current.

Reader's Guide

The 45 nm process represented a critical step in the continuation of Moore's Law, enabling higher transistor densities and improved performance while managing power consumption. Its significance lies in the widespread adoption of high-κ dielectrics and metal gates, which became standard in subsequent nodes. The node also demonstrated the industry's ability to extend optical lithography through double patterning, delaying the need for extreme ultraviolet lithography. The 45 nm process was used in a wide range of processors, including Intel's Core 2 and first-generation Core i3/i5/i7 series, AMD's Phenom II and Opteron lines, and the Xbox 360 S and PlayStation 3 Slim. Its legacy includes setting the stage for the 32 nm and 22 nm nodes, with Intel's 45 nm process achieving a transistor density of 3.33 million transistors per square millimeter.

Did You Know?

• Intel's 45 nm process had a transistor density of 3.33 million transistors per square millimeter.
• Both the Nehalem and Atom microprocessors used six-transistor SRAM cells, not eight-transistor cells.
• TSMC's 40 nm process entered risk production in 2008 and began mass production in 2009.
• Samsung developed a 40 nm process that entered production in 2008, not 2006.

Lithography at the Edge of Physics

The 45 nm node presented a fundamental optical problem: many critical feature sizes fell below the wavelength of the light used to etch them. Both 193 nm and 248 nm wavelengths were in play, yet the features being produced were far smaller than either. To bridge this gap, manufacturers leaned on techniques like larger lenses and, critically, double patterning—a method that effectively etches a pattern twice to achieve spacing a single exposure could not. Intel's approach was particularly notable because it deliberately avoided immersion lithography, instead relying on an explicit line-cutting double patterning strategy that made the lithographic step more demanding. Meanwhile, the industry was shifting previously looser metal layers, such as Metal 4 and Metal 5, from 248 nm to 193 nm exposure, a move expected to push manufacturing costs higher because of the difficulties associated with 193 nm photoresists. The 45 nm node thus became a proving ground for how far dry lithography could be stretched before immersion became unavoidable—a threshold Intel would cross at the 32 nm generation.

The High-κ Dielectric Revolution

One of the most consequential shifts at the 45 nm node was the introduction of high-κ dielectric materials into the transistor gate stack. For years, gate leakage current had been a growing concern as transistors shrank, and the industry initially resisted the idea of swapping the traditional silicon dioxide gate insulator for an entirely new class of material. By 2007, however, that resistance had largely dissolved. Both IBM and Intel announced working high-κ dielectric and metal gate solutions, and Intel went so far as to call the change a fundamental redesign of the transistor itself. NEC also brought high-κ materials into production. In Intel's specific implementation, the gate used a hafnium-based dielectric with a 1 nm equivalent oxide thickness and a 0.7 nm transition layer. The fabrication employed a gate-last process that relied on dummy polysilicon and a damascene metal gate, with gate ends squared off using a second photoresist coating. This was not a minor tweak; it represented a departure from decades of conventional gate engineering and set the template for every subsequent node.

A Staggered Global Rollout

The 45 nm node rolled out across the industry in a staggered but rapid sequence. Matsushita Electric Industrial Co. kicked things off in June 2007, mass-producing system-on-chip designs for digital consumer equipment. Intel followed in November 2007 with the Xeon 5400 series, its first 45 nm processor, after Penryn microarchitecture details had already been unveiled at the April 2007 Intel Developer Forum. AMD entered the fray in late 2008 with a family spanning Sempron II, Athlon II, Turion II, Phenom II, and Shanghai Opteron processors. Beyond the big three, SMIC became the first China-based company to reach 45 nm at the end of 2008, having licensed IBM's bulk process. The node also found its way into consumer electronics: the Xbox 360 S shipped with a 45 nm Xenon processor in 2010, and the PlayStation 3 Slim adopted the Cell Broadband Engine at 45 nm. Meanwhile, TSMC and Samsung had already pushed past to 40 nm, signaling that the 45 nm window would be brief.

Intel's 45 nm Process in Granular Detail

Technical details of Intel's 45 nm process emerged at IEDM 2007 and revealed a design optimized around tight constraints. The gate pitch measured 160 nm—73 percent of the 65 nm generation—while the isolation pitch was 200 nm, only 91 percent of the prior generation, indicating that isolation scaling was slowing. Gate length remained at 35 nm, unchanged from 65 nm. The interconnect stack featured nine layers of carbon-doped oxide with copper, capped by a thick redistribution layer, and contacts were shaped as rectangles rather than circles for local interconnects. A 2008 Chipworks reverse-engineering revealed that trench contacts formed a Metal-0 tungsten layer, with most oriented as short lines parallel to the gates. Drive currents reached 1.36 mA/μm for nFETs and 1.07 mA/μm for pFETs, the latter 51 percent faster than 65 nm thanks to raising germanium content in embedded SiGe stressors from 23 to 30 percent. Perhaps most strikingly, both Nehalem and Atom used eight-transistor SRAM cells instead of the conventional six, incurring an area penalty exceeding 30 percent to better support voltage scaling.