Phase-locked loop
A control system that locks output phase to input phase.
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A phase-locked loop is a feedback control system where the output signal's phase stays locked to the phase of an incoming reference signal. Because phase and frequency are linked, this also means the output frequency maintains a fixed relationship with the input frequency. Adding a frequency divider lets a PLL produce a stable output at a multiple of the input frequency. These capabilities make PLLs useful for tasks like synchronizing clocks, demodulating signals, generating new frequencies, multiplying clock rates, and recovering signals from noisy channels.
Since 1969, complete PLL circuits have been available on a single integrated chip, and modern versions can output frequencies ranging from fractions of a hertz to many gigahertz. As a result, PLLs appear in radios, telecom equipment, computers (for example, distributing precise clock signals inside microprocessors), grid-tie inverters used to connect solar panels and batteries to the power grid, and many other electronic devices.
Quick Facts
- First integrated circuit pll
- 1969 (Signetics NE565, bipolar)
- Early electromechanical pll
- 1921 (Shortt-Synchronome clock)
- Cmos pll integrated circuit
- CD4046 (RCA, a few years after 1969)
Facts from the source article.
Background
Spontaneous synchronization of weakly coupled pendulum clocks was noted by Christiaan Huygens as early as 1673. Around the turn of the 19th century, Lord Rayleigh observed synchronization of weakly coupled organ pipes and tuning forks. In 1919, W. H. Eccles and J. H. Vincent found that two electronic oscillators tuned to slightly different frequencies but coupled to a resonant circuit would soon oscillate at the same frequency. Automatic synchronization of electronic oscillators was described in 1923 by Edward Victor Appleton.
In 1923, Harry Nyquist patented a PLL with a motor-generator as the oscillator. In 1925, David Robertson introduced phase locking in his clock design to control the striking of the bell Great George in the new Wills Memorial Building. Robertson's clock incorporated an electromechanical device that could vary the rate of oscillation of the pendulum, and derived correction signals from a circuit that compared the pendulum phase with that of an incoming telegraph pulse from Greenwich Observatory every morning at 10:00 GMT.
Including equivalents of every element of a modern electronic PLL, Robertson's system was notably ahead of its time in that its phase detector was a relay logic implementation of the transistor circuits for phase/frequency detectors not seen until the 1970s. Robertson's work predated research towards what was later named the phase-lock loop in 1932, when British researchers developed an alternative to Edwin Armstrong's superheterodyne receiver, the Homodyne or direct-conversion receiver.
In the homodyne or synchrodyne system, a local oscillator was tuned to the desired input frequency and multiplied with the input signal. The resulting output signal included the original modulation information. The technique was described in 1932, in a paper by Henri de Bellescize, in the French journal L'Onde Électrique. In analog television receivers since at least the late 1930s, phase-locked-loop horizontal and vertical sweep circuits are locked to synchronization pulses in the broadcast signal.
In 1969, Signetics introduced a line of low-cost monolithic integrated circuits like the NE565 using bipolar transistors, which were complete phase-locked loop systems on a chip, and applications for the technique multiplied. A few years later, RCA introduced the CD4046 Micropower Phase-Locked Loop using CMOS, which also became a popular integrated circuit building block.
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Sources
Compiled from Wikipedia and the sources listed below. Text from Wikipedia is available under CC BY-SA 4.0; this entry is adapted from it.
- Wikipedia: Phase-locked loop (CC BY-SA 4.0).
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