PLL multibit

Lore & Background

A phase-locked loop is a closed-loop system that controls the phase of an oscillator by comparing it with a reference signal. In a unibit PLL, only the most significant bit (MSB) of each counter is used for phase measurement; all other bits are ignored, wasting information. The multibit PLL addresses this by using more bits from the two digital buses—the reference counter bus and the output (VCO) counter bus—to measure phase. This introduces a difficult problem: comparing signals at different frequencies from two counters that count to different final values. Additionally, overflow in the counters disrupts operation, an effect relevant only in multibit PLLs, as unibit PLLs have only a single-bit MSB signal and thus no overflow.

Reader's Guide

The multibit PLL expands the performance envelope of the PLL, enabling faster frequency settling time together with fine frequency resolution and lower phase noise. This is significant because in a unibit PLL, improving one performance criterion—such as frequency resolution—typically degrades others, like settling speed or phase noise. By using more bits, the multibit PLL allows the loop bandwidth to be optimized for phase noise performance or frequency settling speed, with less dependence on frequency resolution. The additional degree of freedom permits adaptation to specific requirements, and early implementations used a microprocessor, microcontroller, or DSP to close the loop. Modern implementations can be realized with programmable logic devices. The improved performance reduces interference among subscribers, enables faster communications with more complex modulation schemes, and lowers transmit power and power consumption in cellular phones and other wireless devices.

Did You Know?

• Overflow in the counters disrupts operation only in multibit PLLs, not in unibit PLLs.
• Multibit PLLs can be implemented with programmable logic devices such as those from Altera Corp.