NVAX

The NVAX is a CMOS microprocessor from Digital Equipment Corporation (DEC) that runs the VAX instruction set. It powered late-model VAX systems introduced in 1991, such as the MicroVAX 3100, VAXstation 4000, VAX 4000, VAX 6000, VAX 7000/10000, and VAXft. A variant called the NVAX+ shares the same microarchitecture but uses a different bus interface and external cache; its bus matches the DECchip 21064, so it can be swapped out for an Alpha processor.

The NVAX die measures 16.2 by 14.6 mm (236.52 mm²) and contains 1.3 million transistors, built on DEC’s CMOS-4 process—a 0.75 μm process with three aluminum interconnect layers. It comes in a 339-pin pin grid array.

Clock speeds for the NVAX are 83.3 MHz (12 ns), 71 MHz (14 ns), and 62.5 MHz (16 ns), delivering about 25 VAX Units of Performance (VUPs). The NVAX+ runs at 90.9 MHz (11 ns) and achieves roughly 35 VUPs, just shy of the VAX 9000 mainframe’s 40 VUPs, but in a desktop form factor. Its 431-pin array and cache system are identical to those on the Alpha, enabling a CPU-level upgrade.

The final model, the NVAX++ (also called NV5), appeared in 1994 in VAX 7000 Model 7x0 and VAX 10000 Model 7x0 systems. It operates at 133 MHz (7.5 ns) on DEC’s CMOS-5 process (0.50 μm) and reaches 50 VUPs. A 170.9 MHz NV5 followed in 1996, used in VAX 7000/10000 Model 8x0 systems. After the NV5, DEC moved entirely to the Alpha architecture.

Microarchitecture

The NVAX’s microarchitecture splits the processor into five semi-autonomous units: the I-box, E-box, F-box, M-box, and C-box. It is macropipelined, handling multiple VAX macroinstructions in parallel, each unit having its own micropipeline.

The I-box fetches and decodes instructions, using a 2 KB direct-mapped virtual instruction cache (VIC) and a 512-entry by 4-bit branch history table, aiming to fetch eight bytes per cycle. The E-box executes most non-floating-point instructions, controlled by microcode from a 1,600-word control store with 20 patchable words. The F-box handles floating-point and 32-bit integer multiply instructions, featuring a four-stage pipeline for floating-point and integer multiply, plus a non-pipelined floating-point divider.